The present invention generally relates to screen printing stencils. The invention has particular utility in depositing solder paste on terminals of a printed circuit board or other electronic substrate.
Microelectronic components can be mounted on printed circuit boards (PCBs) or other substrates in a variety of ways. Originally, most microelectronic components were provided with pins or leads which were passed through openings in the substrate then soldered in place. Increasingly, microelectronic components are being attached to substrates using surface mount technology. In this process, a terminal of the microelectronic component is attached to a terminal carried on a face of the substrate by a solder or the like. Typically, the solder will be applied to a terminal on the substrate as a paste. After the microelectronic component is positioned with its terminal in contact with the solder paste, the solder paste will be heated, causing it to reflow and electrically connect the two terminals.
Printed circuit boards and other microelectronic substrates are often manufactured in multi-step processes. The terminals are typically arranged on a face of the substrate in a predetermined array such that the individual terminals are in the locations where they are desired in the final end product. After the terminal array is initially formed on the substrate, the substrate may be subjected to a number of additional manufacturing steps. These subsequent manufacturing steps can induce dimensional changes in the substrate which alter the relative positions of the terminals in the initial terminal array, leading to a distorted terminal array in the final substrate.
For example, PCBs typically comprise multi-layer laminates, with selected layers bearing a subset of the complete electronic circuitry of the PCB. The layers are physically stacked on top of one another and laminated together. This laminating process frequently involves one or more steps in which the PCB is heated to elevated temperatures to bond the layers to one another. This thermal cycling and other handling of the PCB during manufacture will cause the PCB to change in shape, shifting the relative orientations of the terminals in the initially applied terminal array.
These shifts in position of the terminals on the substrates can cause significant manufacturing difficulties. Typically, the solder paste used to join the substrate terminals to terminals on the microelectronic components is applied in a screening process. In this process, a stencil is positioned over the terminal-bearing surface of the substrate, with the stencil being aligned with the substrate in a predetermined orientation. The orifices in the stencil are arranged in an array which matches each orifice to a terminal in the initial terminal array. Unfortunately, the growth or shrinkage of the substrate distorts the terminal array, so alignment of the orifices in the stencil with the corresponding terminals of the substrate can no longer be assured. Improper registry of the stencil orifice with the corresponding terminal on the substrate can lead to a faulty connection between the substrate and the microelectronic component mounted thereon. For more significant alterations in the substrate, solder paste intended for one terminal may bridge the gap between the intended terminal and another adjacent terminal, leading to a short circuit in the final product. After the solder paste is applied, the solder paste may be heated to cause it to xe2x80x9creflowxe2x80x9d then allowed to cool, mechanically and electronically connecting the microelectronic component to the substrate.
The present invention provides stencils for use in screen printing and various related structures; methods for applying solder on electronic substrates using a stencil; and methods and devices for designing stencils for applying solder paste on electronic substrates. In accordance with one embodiment of the invention, a printing stencil is adapted for registration with an electronic substrate, such as a PCB, about a locus. The stencil includes a stencil body and an array of printing orifices passing through the stencil body. The printing orifices have varying sizes, with the size of each printing orifice being a function of a distance of the printing orifice from the locus. If so desired, the locus may be the center of the stencil body.
A stencil in accordance with another embodiment of the invention is adapted for applying solder to terminals of a terminal array carried by an electronic substrate. Such a stencil may include a stencil body having a center and an array of solder orifices passing through the stencil body. At least one central solder orifice of the array has a first size. Other solder orifices of the array can have a size different from the first size, with the increase or decrease in size being determined by a size scaling factor. In this embodiment, the size scaling factor for each such larger or smaller solder orifice is proportional to a distance of the solder orifice from the center of the stencil body.
Another embodiment of the invention provides a stencil adapted for registration with an electronic substrate, the substrate bearing an array of terminals, and the terminals in the array having an initial relative orientation in an initial terminal array. This stencil includes a stencil body and an array of printing orifices passing through a thickness of the stencil body. Each of the printing orifices in this particular embodiment is displaced by a predetermined offset from the center of the stencil body. For example, the offset for each printing orifice can be proportional to a distance of the orifice from the center.
Yet another embodiment of the invention provides a stencil in which both the size and the position of the printing orifices have been adjusted. The stencil of this embodiment includes a stencil body, a locus, and a plurality of printing orifices in the stencil body. The size of each printing orifice can be correlated to a first size by a size scaling factor. The position of each printing orifice can be displaced by a position-scaling factor from a position corresponding to a position of an associated terminal in the initial terminal array. The size scaling factor and the position-scaling factor for each printing orifice can both be proportional to a distance of the orifice from the locus.
A subassembly for manufacturing an electronic device in accordance with another embodiment of the invention includes an electronic substrate and a stencil. The electronic substrate has a first surface, a substrate locus, circuitry, and a plurality of terminals carried on the first surface and electrically coupled to the circuitry. The terminals have moved with respect to one another from an initial terminal array of target positions in which the targets had a first relative position to a stenciling array of target positions in which the targets have a second relative position. The stencil has a second surface, a stencil locus, and a plurality of solder orifices extending through a thickness of the stencil. Each of the solder orifices is displaced by a predetermined offset from a position corresponding to a position of an associated terminal in the initial terminal array. The offset for each solder orifice is proportional to a distance of the solder orifice from the stencil locus. The second surface of the stencil is juxtaposed with the first surface of the substrate and the stencil locus is registered with the substrate locus.
Other embodiments of the invention provide methods of screen printing which are well suited for applying solder paste on an electronic substrate using a stencil. In accordance with one such method, an electronic substrate is provided, with the electronic substrate including a substrate body and a plurality of terminals. The substrate body has circuitry, a first surface, and a substrate locus. The terminals are electrically coupled to the circuitry and are carried on the first surface in a predetermined relative relationship to define an initial terminal array. The substrate body is dimensionally altered such that the relative relationship of the terminals differs from the predetermined relative relationship. A stencil is also provided, with the stencil having a stencil body, a second surface, a stencil locus, and a plurality of solder orifices passing through the stencil body. Each solder orifice has a size correlated to an ideal size by a size scaling factor. The size scaling factor can be proportional to a distance from the stencil locus. If so desired, the position of each solder orifice may also be displaced by a position scaling factor from a position corresponding to a position of an associated terminal in the initial terminal array. Such a position-scaling factor may also be proportional to a distance from the stencil locus. The first surface of the electronic substrate and a second surface of the stencil are juxtaposed, with the stencil locus in registry with the substrate locus. The solder is passed through the solder orifices in the stencil to deposit a discrete volume of solder paste on each of the corresponding terminals.
Another embodiment of the invention provides a method for designing a stencil which may be used for applying solder paste on a plurality of like electronic substrate. In accordance with this method, the initial positions of a plurality of electrically conductive terminals are determined, with the terminals being arranged in an initial terminal array to be carried by the substrates. A size scaling factor and, if so desired, a position scaling constant for the initial terminal array may be estimated in light of anticipated handling of the substrates prior to solder deposition. A stencil locus of the stencil is identified. This stencil locus may be the center of the stencil or another point on the stencil. A plurality of solder orifices are arranged, with a separate solder orifice corresponding to each terminal. An initial solder orifice size is selected to deliver an appropriate volume of solder paste to an underlying terminal. Each solder orifice may then be sized by multiplying the initial solder orifice size by a size scaling factor proportional to the size scaling constant. The size scaling factor may be 1.0 adjacent the stencil locus and increase outwardly therefrom in proportion to a distance of the orifice from the stencil locus. In a further adaptation of this method, the positions of the solder orifices may also be adjusted by displacing each solder orifice from an ideal position by a predetermined offset correlated to the position scaling constant. The ideal position for each solder orifice may correspond to a position of the corresponding target in the initial target array. The position-scaling factor for each orifice can be proportional to a distance of the orifice from the stencil locus.
Another embodiment of the invention provides a computer readable storage medium containing a computer readable code for operating the computer to design a stencil as noted above. A further embodiment provides a system for designing a stencil, the system including a memory circuit, a computer readable storage medium containing program instructions for execution by a processor, and a processor connected the memory circuit and the computer readable storage medium, with the processor executing the program instructions stored on the computer readable medium to design a stencil.